1. Technical Field
The present invention relates to an integrated circuit with integrated testing circuits, and, more particularly, to a chip level diagnostic apparatus incorporating a scan design integrated latch-based system.
2. Description of the Related Art
The testing of the integrated circuits is well known in the art. Testing is necessary so chip designers can be assured that their designs work properly. The designers desire observability, which refers to the ease with which the state of internal signals in the IC can be determined. Furthermore, the designers require controllability, which refers to the ease of producing a specific internal signal value. Designers obtain observability or controllability in a circuit design by introducing test points, or additional circuit inputs and outputs, into the chip for use during testing. For circuit boards, the cost of test points is often well justified. On the other hand, the cost of test points for ICs can be prohibitive because of IC pin limitations. Consequently, techniques have evolved that use scan paths to provide access to the internal nodes of a circuit without requiring a separate external connection for each node accessed.
In the scan path technique, a circuit is designed so that it has two modes of operation: one that is the normal functional mode, and the other that is the test mode, in which circuit memory (storage) elements, typically combinational circuitry input and output storage elements, are interconnected into a shift register chain for forming scan units associated with each set of combinational logic. With the circuit in a test mode, it is possible to shift an arbitrary test pattern into the input elements. By returning the circuit to a normal mode, the combinational circuitry can act upon the shift register contents and then store the results in the output elements. If the circuit is then placed into a test mode, it is possible to shift out the contents of the shift register and compare the contents with the correct response. One way of implementing a scan path is to interconnect the circuit flipflops to form a shift register.
One example of the scan path technique is "level sensitive scan design" (LSSD), used by International Business Machines Incorporated (IBM). Unfortunately, LSSD scan paths also have certain limitations. One limitation is that with LSSD design, any random pattern of values may appear in the latches, both during the scanning operation and as input values for any test. These random patterns, however, may not be permitted at certain times. The most common case is when the latches hold control signals to a pass-gate multiplexor (MUX). These signals must be mutually exclusive or else an excessive amount of current may conduct, possibly causing damage, since one selected gate may be pulling a node towards a VDD voltage while another is pulling it down to ground. Even if no damage occurs, the node may have an indeterminate value, so that the output values cannot be predicted for that test.
Similarly, if none of the control signals is active, then none of the gates is selected and the internal node may be in a high impedance mode, which is also indeterminate. While such indeterminate values can either be avoided or ignored by software programs, which generate the test, such indeterminate values can neither be prevented nor ignored when the latches are scanned during self-test operations. A set of signals that are mutually exclusive, such that one and only one is active at any time, are said to be "orthogonal".
Accordingly, what is needed is an LSSD logic that does not affect the functional behavior of the circuits, but which does affect the behavior during scanning. Additionally, the LSSD logic must not affect the speed of the chip during normal functional operations. Further, the LSSD logic must minimize the amount of chip real estate normally taken for the testing devices implemented thereon.